An Efficient Memory System for the SIMD Construction of a Gaussian Pyramid
IEEE Transactions on Parallel and Distributed Systems
Instruction Set Extensions for MPEG-4 Video
Journal of VLSI Signal Processing Systems - Special issue on implementation of MPEG-4 multimedia codecs
An Efficient Buffer Memory System for Subarray Access
IEEE Transactions on Parallel and Distributed Systems
Computer Architecture: Concepts and Evolution
Computer Architecture: Concepts and Evolution
DFT '00 Proceedings of the 15th IEEE International Symposium on Defect and Fault-Tolerance in VLSI Systems
The MOLEN rho-mu-Coded Processor
FPL '01 Proceedings of the 11th International Conference on Field-Programmable Logic and Applications
Memory Organization of a Single-Chip Video Signal Processing System with Embedded DRAM
GLS '99 Proceedings of the Ninth Great Lakes Symposium on VLSI
VLSID '00 Proceedings of the 13th International Conference on VLSI Design
Memory Systems for Image Processing
IEEE Transactions on Computers
Access and Alignment of Data in an Array Processor
IEEE Transactions on Computers
The Organization and Use of Parallel Memories
IEEE Transactions on Computers
IEEE Transactions on Multimedia
A flexible parallel architecture adapted to block-matching motion-estimation algorithms
IEEE Transactions on Circuits and Systems for Video Technology
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This paper discusses architectural solutions that deal with the high data throughput and the high computational power - two crucial performance requirements of MPEG standards. To increase the data throughput, we define a new data storage facility with a specific data organization and a new addressing mode. More specifically, we introduce an addressing function and refer to it as two-dimensional block addressing. Furthermore, we propose such an addressing approach, as an architectural feature and we believe it has useful properties that may position it as a basic addressing mode in future multimedia architectures. In addition, we propose an instruction set extension, utilizing the advantages of this addressing mode, as means of improving the computational power of a general-purpose super-scalar processor. To illustrate this concept, we have implemented a new instruction "ACcepted Quality" as a dedicated systolic structure. This instruction supports the corresponding function "ACQ" as defined in the Verification Model of MPEG-4. Its FPGA realization suggests 62 ns operating latency. Utilizing this result, we have made performance evaluations with a benchmark software (MPEG-4 shape encoder) using a cycle-accurate simulator. The simulation results indicate that the performance is increased by up to 10%. The introduced approach can be utilized by data encoding tools, which are based on block division of data. These tools are an essential part of many recent and up coming visual data compression standards like MPEG-4.