An Efficient Memory System for Image Processing
IEEE Transactions on Computers
Survey of Commercial Parallel Machines
Survey of Commercial Parallel Machines
An Efficient Buffer Memory System for Subarray Access
IEEE Transactions on Parallel and Distributed Systems
A 2D Addressing Mode for Multimedia Applications
Embedded Processor Design Challenges: Systems, Architectures, Modeling, and Simulation - SAMOS
A 2D addressing mode for multimedia applications
Embedded processor design challenges
Configurable parallel memory architecture for multimedia computers
Journal of Systems Architecture: the EUROMICRO Journal
Multiaccess Memory System for Attached SIMD Computer
IEEE Transactions on Computers
Hi-index | 0.01 |
In this paper, a memory system is introduced for the efficient construction of a Gaussian pyramid. The memory system consists of an address calculating circuit, an address routing circuit, a memory module selection circuit, and $2^n+1$ memory modules. The memory system provides parallel access to $2^n$ image points whose patterns are a block, a row or a column, where the interval of the column and the block is 1 and the interval of the row is $2^l,l\ge 0.$.The performance of a generic SIMD(Single-Instruction Multiple-Data) processor using the proposed memory system is compared with one using an interleaved memory system for the construction of a Gaussian pyramid. The ratio of the time of the construction of level 2 and level 10 from the original image (level 0) of an SIMD processor with an interleaved memory system to that of the proposed memory system is 1.485 and 1.633, respectively.