Memory Organization of a Single-Chip Video Signal Processing System with Embedded DRAM

Authors:
Jörg Hilgenstock;Klaus Herrmann;Peter Pirsch
Affiliations:
-;-;-
Venue:
GLS '99 Proceedings of the Ninth Great Lakes Symposium on VLSI
Year:
1999

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Abstract

A programmable single-chip multiprocessor system for video coding applications has been developed. It integrates four processing elements, on-chip DRAM, and application-specific interfaces. The integrated DRAM is primarily used as frame buffer and makes external memory for most applications obsolete. For fast access to local data segments also static RAM is integrated in each processing element.