A Characterization of Ten Hidden-Surface Algorithms
ACM Computing Surveys (CSUR)
Fast parallel sorting algorithms
Communications of the ACM
Texture and reflection in computer generated images
Communications of the ACM
Hidden surface removal using polygon area sorting
SIGGRAPH '77 Proceedings of the 4th annual conference on Computer graphics and interactive techniques
X-Tree: A tree structured multi-processor computer architecture
ISCA '78 Proceedings of the 5th annual symposium on Computer architecture
The notion of quantitative invisibility and the machine rendering of solids
ACM '67 Proceedings of the 1967 22nd national conference
Pixel-planes 5: a heterogeneous multiprocessor graphics system using processor-enhanced memories
SIGGRAPH '89 Proceedings of the 16th annual conference on Computer graphics and interactive techniques
PixelFlow: high-speed rendering using image composition
SIGGRAPH '92 Proceedings of the 19th annual conference on Computer graphics and interactive techniques
Accommodating memory latency in a low-cost rasterizer
HWWS '97 Proceedings of the ACM SIGGRAPH/EUROGRAPHICS workshop on Graphics hardware
Hardware accelerated rendering of antialiasing using a modified a-buffer algorithm
Proceedings of the 24th annual conference on Computer graphics and interactive techniques
Fast image generation of construcitve solid geometry using a cellular array processor
SIGGRAPH '85 Proceedings of the 12th annual conference on Computer graphics and interactive techniques
Fast spheres, shadows, textures, transparencies, and imgage enhancements in pixel-planes
SIGGRAPH '85 Proceedings of the 12th annual conference on Computer graphics and interactive techniques
Hybrid sort-first and sort-last parallel rendering with a cluster of PCs
HWWS '00 Proceedings of the ACM SIGGRAPH/EUROGRAPHICS workshop on Graphics hardware
High-performance polygon rendering
SIGGRAPH '88 Proceedings of the 15th annual conference on Computer graphics and interactive techniques
A frame buffer system with enhanced functionality
SIGGRAPH '81 Proceedings of the 8th annual conference on Computer graphics and interactive techniques
Simulation and expected performance analysis of multiple processor Z-buffer systems
SIGGRAPH '80 Proceedings of the 7th annual conference on Computer graphics and interactive techniques
On visible surface generation by a priori tree structures
SIGGRAPH '80 Proceedings of the 7th annual conference on Computer graphics and interactive techniques
A parallel processor system for three-dimensional color graphics
SIGGRAPH '84 Proceedings of the 11th annual conference on Computer graphics and interactive techniques
Parallel polygon rendering on the graphics computer VC-1
PAS '95 Proceedings of the First Aizu International Symposium on Parallel Algorithms/Architecture Synthesis
Compilers, architectures and synthesis for embedded computing: retrospect and prospect
CASES '10 Proceedings of the 2010 international conference on Compilers, architectures and synthesis for embedded systems
Review: Large scale distributed visualization on computational Grids: A review
Computers and Electrical Engineering
A multi-processor workstation with a logic-enhanced distributed frame buffer
EGGH'87 Proceedings of the Second Eurographics conference on Advances in Computer Graphics Hardware
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Presented is the design of a flexible expandable multi-processor system for video graphics and image processing. The design involves a central controller which broadcasts data to a variable number of independently executing processing units, each of which in turn controls a variable number of memory units among which the video (frame buffer) image is distributed. An interleaved addressing organization of the video memories guarantees both an even workload distribution as well as maintenance of image coherence for each processing element. Execution speed and image resolution can be independently altered (at any time) by varying the number of processing and memory units. Sample applications of the system—for rapid line drawing and “electronic scene generation” (visible surface algorithms)—are described. Variations of the design for low cost and for powerful, real-time configurations are outlined.