An expandable multiprocessor architecture for video graphics (Preliminary Report)
ISCA '79 Proceedings of the 6th annual symposium on Computer architecture
The use of grayscale for improved raster display of vectors and characters
SIGGRAPH '78 Proceedings of the 5th annual conference on Computer graphics and interactive techniques
SIGGRAPH '79 Proceedings of the 6th annual conference on Computer graphics and interactive techniques
Simulation and expected performance analysis of multiple processor Z-buffer systems
SIGGRAPH '80 Proceedings of the 7th annual conference on Computer graphics and interactive techniques
Dynamic scan-converted images with a frame buffer display device
SIGGRAPH '80 Proceedings of the 7th annual conference on Computer graphics and interactive techniques
Real time animation playback on a frame store display system
SIGGRAPH '80 Proceedings of the 7th annual conference on Computer graphics and interactive techniques
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A video-resolution frame buffer system with 32 bits per pixel is described. The system includes, in addition to standard features for limited zoom and pan, an arithmetic unit at the update port which allows local computation of many frequently-used pixel-level functions combining stored pixel values with incoming pixel values. In addition to the standard arithmetic and logical functions there are functions for sum to maximum pixel value and difference to minimum pixel value. Comparisons between incoming and stored data are used to implement conditional writes based on depth values for depth-buffer algorithms. Update and refresh ports are designed for a wide range of flexibility allowing simultaneous use by separate tasks and various functional rearrangements of the 32-bit pixel words. The memory architecture, refresh and update ports are described. Examples of widely divergent modes of operation are provided.