Principles of interactive computer graphics (2nd ed.)
Principles of interactive computer graphics (2nd ed.)
A Characterization of Ten Hidden-Surface Algorithms
ACM Computing Surveys (CSUR)
The aliasing problem in computer-generated shaded images
Communications of the ACM
Communications of the ACM
An expandable multiprocessor architecture for video graphics (Preliminary Report)
ISCA '79 Proceedings of the 6th annual symposium on Computer architecture
Distributing a visible surface algorithm over multiple processors
ACM '77 Proceedings of the 1977 annual conference
An introduction to the N. mPc design environment
DAC '79 Proceedings of the 16th Design Automation Conference
The pixel machine: a parallel image computer
SIGGRAPH '89 Proceedings of the 16th annual conference on Computer graphics and interactive techniques
A characterization of ten rasterization techniques
SIGGRAPH '89 Proceedings of the 16th annual conference on Computer graphics and interactive techniques
“Topologies”—distributed objects on multicomputers
ACM Transactions on Computer Systems (TOCS)
Parallel object-space hidden surface removal
SIGGRAPH '90 Proceedings of the 17th annual conference on Computer graphics and interactive techniques
PixelFlow: high-speed rendering using image composition
SIGGRAPH '92 Proceedings of the 19th annual conference on Computer graphics and interactive techniques
A MIMD rendering algorithm for distributed memory architectures
PRS '93 Proceedings of the 1993 symposium on Parallel rendering
A multicomputer polygon rendering algorithm for interactive applications
PRS '93 Proceedings of the 1993 symposium on Parallel rendering
A Sorting Classification of Parallel Rendering
IEEE Computer Graphics and Applications
A New Algorithm for Interactive Graphics on Multicomputers
IEEE Computer Graphics and Applications
Hardware accelerated rendering of antialiasing using a modified a-buffer algorithm
Proceedings of the 24th annual conference on Computer graphics and interactive techniques
Load balancing for multi-projector rendering systems
HWWS '99 Proceedings of the ACM SIGGRAPH/EUROGRAPHICS workshop on Graphics hardware
Fast image generation of construcitve solid geometry using a cellular array processor
SIGGRAPH '85 Proceedings of the 12th annual conference on Computer graphics and interactive techniques
Hybrid sort-first and sort-last parallel rendering with a cluster of PCs
HWWS '00 Proceedings of the ACM SIGGRAPH/EUROGRAPHICS workshop on Graphics hardware
DAC '83 Proceedings of the 20th Design Automation Conference
DAC '83 Proceedings of the 20th Design Automation Conference
A parallel scan conversion algorithm with anti-aliasing for a general-purpose ultracomputer
SIGGRAPH '83 Proceedings of the 10th annual conference on Computer graphics and interactive techniques
Parallel processing image synthesis and anti-aliasing
SIGGRAPH '81 Proceedings of the 8th annual conference on Computer graphics and interactive techniques
A frame buffer system with enhanced functionality
SIGGRAPH '81 Proceedings of the 8th annual conference on Computer graphics and interactive techniques
A system design revolution (Panel Session)
SIGGRAPH '81 Proceedings of the 8th annual conference on Computer graphics and interactive techniques
A parallel processor system for three-dimensional color graphics
SIGGRAPH '84 Proceedings of the 11th annual conference on Computer graphics and interactive techniques
Hexagonal storage scheme for interleaved frame buffers and textures
Proceedings of the ACM SIGGRAPH/EUROGRAPHICS conference on Graphics hardware
VLSI drawing processor utilizing multiple parallel scan-line processors
EGGH'87 Proceedings of the Second Eurographics conference on Advances in Computer Graphics Hardware
A multi-processor workstation with a logic-enhanced distributed frame buffer
EGGH'87 Proceedings of the Second Eurographics conference on Advances in Computer Graphics Hardware
Towards a taxonomy for display processors
EGGH'89 Proceedings of the Fourth Eurographics conference on Advances in Computer Graphics Hardware
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The results of expected performance analysis and simulation of three multiple processor Z-buffer architectures are presented. These architectures have been proposed as approaches to applying many processors, working in parallel, to the task of rapidly creating shaded raster images. These architectures are attractive since they offer potentially high performance, in terms of image update rate, at modest cost. All three approaches make use of multiple instances of identical processor modules. The analyses and simulations indicate that substantial gain is possible by applying multiple processors to the task. But, as more and more processors are added, additional gains in performance become smaller and smaller. This result suggests optimal system sizes. The performance of these architectures depends on the processors used, the number of processors, and certain characteristics of the image environments. Each architecture has its own performance characteristics and limitations.