Sphere-packings, lattices, and groups
Sphere-packings, lattices, and groups
The pixel machine: a parallel image computer
SIGGRAPH '89 Proceedings of the 16th annual conference on Computer graphics and interactive techniques
Computer graphics: principles and practice (2nd ed.)
Computer graphics: principles and practice (2nd ed.)
A Sorting Classification of Parallel Rendering
IEEE Computer Graphics and Applications
The sort-first rendering architecture for high-performance graphics
I3D '95 Proceedings of the 1995 symposium on Interactive 3D graphics
VC-1: a scalable graphics computer with virtual local frame buffers
SIGGRAPH '96 Proceedings of the 23rd annual conference on Computer graphics and interactive techniques
The design and analysis of a cache architecture for texture mapping
Proceedings of the 24th annual international symposium on Computer architecture
Prefetching in a texture cache architecture
HWWS '98 Proceedings of the ACM SIGGRAPH/EUROGRAPHICS workshop on Graphics hardware
HWWS '99 Proceedings of the ACM SIGGRAPH/EUROGRAPHICS workshop on Graphics hardware
Tiled polygon traversal using half-plane edge functions
HWWS '00 Proceedings of the ACM SIGGRAPH/EUROGRAPHICS workshop on Graphics hardware
Incremental and hierarchical Hilbert order edge equation polygon rasterizatione
Proceedings of the ACM SIGGRAPH/EUROGRAPHICS workshop on Graphics hardware
Principles of Digital Image Synthesis
Principles of Digital Image Synthesis
A Multiaccess Frame Buffer Architecture
IEEE Transactions on Computers
Comments on "A Multiaccess Frame Buffer Architecture"
IEEE Transactions on Computers
Simulation and expected performance analysis of multiple processor Z-buffer systems
SIGGRAPH '80 Proceedings of the 7th annual conference on Computer graphics and interactive techniques
Distributing a visible surface algorithm over multiple processors
ACM '77 Proceedings of the 1977 annual conference
Hexagonal Raster for Computer Graphic
IV '00 Proceedings of the International Conference on Information Visualisation
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This paper presents a storage scheme which statically assigns pixel/texel coordinates to multiple memory banks in order to minimize frame buffer and texture memory access load imbalance. In this scheme, the pixels stored in a particular memory bank are placed at the center and the vertices of hexagons packed in the frame buffer By making these hexagons close to regular so that the pixel placement is uniform and isotropic, frame buffer and texture memory accesses are evenly distributed over the memory banks. The analysis of memory access patterns in rendering typical 3D graphics scenes shows that the hexagonal storage scheme can reduce rendering performance degradation due to bank conflicts by an average of 10% compared to the traditional rectangular storage scheme.