VLSI-architectures for computer graphics
Advances in computer graphics I
The Feasibility of a VLSI Chip for Ray Tracing Bicublic Patches
IEEE Computer Graphics and Applications
An exact incremental hidden surface removal algorithm
Advances in computer graphics hardware II
Ray tracing rational B-spline patches in VLSI
Advances in computer graphics hardware II
A vector-like architecture for raster graphics
Advances in computer graphics hardware II
A processor for an object-oriented rendering system
Computer Graphics Forum
Computer graphics hardware
Fast spheres, shadows, textures, transparencies, and imgage enhancements in pixel-planes
SIGGRAPH '85 Proceedings of the 12th annual conference on Computer graphics and interactive techniques
A Characterization of Ten Hidden-Surface Algorithms
ACM Computing Surveys (CSUR)
A parallel algorithm for polygon rasterization
SIGGRAPH '88 Proceedings of the 15th annual conference on Computer graphics and interactive techniques
IEEE Computer Graphics and Applications
What We Need Around Here is More Aliasing
IEEE Computer Graphics and Applications
IEEE Computer Graphics and Applications
Effektives Anti-Aliasing für die Bilderzeugung auf Rastersichtgeräten
Visualisierungstechniken und Algorithmen, Fachgespräch
PROOF: An Architecture for Rendering in Object Space
Advances in Computer Graphics Hardware III (Eurographics'88 Workshop)
The Geometry Engine: A VLSI Geometry System for Graphics
SIGGRAPH '82 Proceedings of the 9th annual conference on Computer graphics and interactive techniques
Towards a taxonomy of computer architecture based on the machine data type view
ISCA '83 Proceedings of the 10th annual international symposium on Computer architecture
Simulation and expected performance analysis of multiple processor Z-buffer systems
SIGGRAPH '80 Proceedings of the 7th annual conference on Computer graphics and interactive techniques
The A -buffer, an antialiased hidden surface method
SIGGRAPH '84 Proceedings of the 11th annual conference on Computer graphics and interactive techniques
SIGGRAPH '84 Proceedings of the 11th annual conference on Computer graphics and interactive techniques
System architecture for high-performance vector graphics
System architecture for high-performance vector graphics
A hierarchical model of a graphics system
ACM SIGGRAPH Computer Graphics
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Image generation for raster displays proceeds in two main steps: geometry processing and pixel processing. The snbsystem performing the pixel processing is called display processor. In the paper a model for the display processor is developed that takes into account both function and timing properties. The model identifies scan conversion, hidden surface removal, shading and anti-aliasing as tile key functions of the display processor. The timing model is expressed in an in equation being fundamental for all display processor architectures. On the basis of that model a taxonomy is presented which classifies display processors according to four main criteria: function, partitioning, architecture and performance. The taxonomy is applied to five real display processors: Pixel-planes, SLAM, PROOF, the Ray-Casting Machine and the Structured Frame Store System. Investigation of existing display processor architectures on the basis of the developed taxonomy revealed a potential new architecture. This architecture partitions the image generation process in image space and employs a tree topology.