An introduction to digital image processing
An introduction to digital image processing
A parallel processor architecture for graphics arithmetic operations
SIGGRAPH '87 Proceedings of the 14th annual conference on Computer graphics and interactive techniques
Pixel-planes 5: a heterogeneous multiprocessor graphics system using processor-enhanced memories
SIGGRAPH '89 Proceedings of the 16th annual conference on Computer graphics and interactive techniques
A characterization of ten rasterization techniques
SIGGRAPH '89 Proceedings of the 16th annual conference on Computer graphics and interactive techniques
Computer graphics: principles and practice (2nd ed.)
Computer graphics: principles and practice (2nd ed.)
Advances in Computer Graphics Hardware II (Eurographics'87 Workshop)
Combining Z-buffer Engines for Higher-Speed Rendering
Advances in Computer Graphics Hardware III (Eurographics'88 Workshop)
A VLSI Architecture for Image Composition
Advances in Computer Graphics Hardware III (Eurographics'88 Workshop)
Anti-aliased line drawing using brush extrusion
SIGGRAPH '83 Proceedings of the 10th annual conference on Computer graphics and interactive techniques
The Geometry Engine: A VLSI Geometry System for Graphics
SIGGRAPH '82 Proceedings of the 9th annual conference on Computer graphics and interactive techniques
The use of grayscale for improved raster display of vectors and characters
SIGGRAPH '78 Proceedings of the 5th annual conference on Computer graphics and interactive techniques
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One of the principle drawbacks with traditional parallel image composition architectures is the lack of support for transparent images. This paper introduces the Distributed Cell Store System, an architecture based on image composition principles, but which provides explicit support for transparency via its Serial Bus System. The transparency support is exploited in a scheme for the generation of smooth-edged lines, which avoids the need for any anti-aliasing calculation in software. The benefits of segmenting lines so that different segments may be rendered in parallel in different processing units are identified and quantified, and the paper concludes with a discussion on the benefits for incremental image specification systems which could be gained from implementation on such a hardware platform.