GigaNoC - A Hierarchical Network-on-Chip for Scalable Chip-Multiprocessors

Authors:
Christoph Puttmann;Jorg-Christian Niemann;Mario Porrmann;Ulrich Ruckert
Affiliations:
University of Paderborn, Germany;Johannes Heidenhain GmbH Traunreut, Germany;University of Paderborn, Germany;University of Paderborn, Germany
Venue:
DSD '07 Proceedings of the 10th Euromicro Conference on Digital System Design Architectures, Methods and Tools
Year:
2007

Citing 0
Cited 3

Run-time reconfigurability in embedded multiprocessors

ACM SIGARCH Computer Architecture News
HiRA: A methodology for deadlock free routing in hierarchical networks on chip

NOCS '09 Proceedings of the 2009 3rd ACM/IEEE International Symposium on Networks-on-Chip
Handling global traffic in future CMP NoCs

Proceedings of the International Workshop on System Level Interconnect Prediction

Quantified Score

Hi-index	0.00

Visualization

Abstract

Electrical engineers have learned how to build amazingly complex systems by assembling transistors, wires, and passive components into intricate networks. While solidly founded in semiconductor physics, pure engineering has made possible the design of ...