A fast and low cost testing technique for core-based system-on-chip
DAC '98 Proceedings of the 35th annual Design Automation Conference
A performance comparison of multi-hop wireless ad hoc network routing protocols
MobiCom '98 Proceedings of the 4th annual ACM/IEEE international conference on Mobile computing and networking
Route packets, not wires: on-chip inteconnection networks
Proceedings of the 38th annual Design Automation Conference
Introduction to Algorithms
A structured test re-use methodology for core-based system chips
ITC '98 Proceedings of the 1998 IEEE International Test Conference
A structured and scalable mechanism for test access to embedded reusable cores
ITC '98 Proceedings of the 1998 IEEE International Test Conference
VTS '04 Proceedings of the 22nd IEEE VLSI Test Symposium
The feasibility of on-chip interconnection using antennas
ICCAD '05 Proceedings of the 2005 IEEE/ACM International conference on Computer-aided design
Bringing communication networks on a chip: test and verification implications
IEEE Communications Magazine
IEEE Transactions on Computer-Aided Design of Integrated Circuits and Systems
Multi-hop communications on wireless network-on-chip using optimized phased-array antennas
Computers and Electrical Engineering
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The rapid migration to nanometer design processes has brought an unprecedented level of integration by allowing system designers to pack a wide variety of functionalities on-chip, namely, systems-on-a-chip (SoCs). In the meantime, electronic testing becomes an enabling technology for this SoC paradigm, since the integration of various core tests is a big challenge, and has revealed a widening gap between design and manufacturing. In particular, the increasing complexity and density of nanometer SoCs have led to the problem of visibility and accessibility in testing. In this paper, we propose an integrated wireless test framework to resolve the acerbated core accessibility problem and to eliminate the incompatibility between the existing SoC test strategies and the next generation billion-transistor SoC specification. Under such a test strategy, the intra-chip wireless links form the wireless test access mechanism (TAM) to transport test data chip-wide. We present a self-configurable multi-hop wireless test micronetwork, dubbed MTNet, with simple and efficient data transmission protocols, and develop a system level design-for-testability structure. Consequently, we propose a geographic routing algorithm to find the test access paths for the deeply embedded cores and a path driven test scheduling algorithm to design and integrate the MTNet-based SoC test access architecture. Extensive simulation study show the feasibility and applicability of MTNet.