A novel pipelining scheme for network-on-chip router

Authors:
Zhe Zhang;Xiaoming Hu
Affiliations:
School of Computer and Information, Shanghai Second Polytechnic University, Shanghai, China;School of Computer and Information, Shanghai Second Polytechnic University, Shanghai, China
Venue:
IITA'09 Proceedings of the 3rd international conference on Intelligent information technology application
Year:
2009

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Abstract

Design of high-performance router is one of the greatest challenges facing Network-on-Chip (NoC). A 5-stage pipelining scheme was proposed for wormhole router in NoC. It originates from the canonical 4-stage pipelining scheme, and had the longest stage for virtual-channel allocation in the ancestor split into two stages. The 5-stage pipelining scheme may boost the maximum frequency of the router and NoC, rather than shorten the pipeline and lower the maximum frequency in the well-known 3-stage scheme. As NoC allows high frequency and GALS (global asynchronous and local synchronous) is advocated in present chip design, the proposed 5-stage pipelining scheme is to be a viable option for NoC router. The performances of above three pipelining schemes were quantified, and the proposed scheme was shown to lead the network to achieve the lowest average packet latency and the highest throughput.