Express Cubes: Improving the Performance of k-ary n-cube Interconnection Networks
IEEE Transactions on Computers
The hyper-ring network: a cost-efficient topology for scalable multicomputers
SAC '98 Proceedings of the 1998 ACM symposium on Applied Computing
Interconnect scaling implications for CAD
ICCAD '99 Proceedings of the 1999 IEEE/ACM international conference on Computer-aided design
Interconnection Networks: An Engineering Approach
Interconnection Networks: An Engineering Approach
Computer
A Performance Comparison of Hierarchical Ring- and Mesh- Connected Multiprocessor Networks
HPCA '97 Proceedings of the 3rd IEEE Symposium on High-Performance Computer Architecture
A Delay Model and Speculative Architecture for Pipelined Routers
HPCA '01 Proceedings of the 7th International Symposium on High-Performance Computer Architecture
Principles and Practices of Interconnection Networks
Principles and Practices of Interconnection Networks
Simulation and analysis of network on chip architectures: ring, spidergon and 2D mesh
Proceedings of the conference on Design, automation and test in Europe: Designers' forum
Interconnect design considerations for large NUCA caches
Proceedings of the 34th annual international symposium on Computer architecture
Enabling Technology for On-Chip Interconnection Networks
NOCS '07 Proceedings of the First International Symposium on Networks-on-Chip
A Hybrid Ring/Mesh Interconnect for Network-on-Chip Using Hierarchical Rings for Global Routing
NOCS '07 Proceedings of the First International Symposium on Networks-on-Chip
The cube-connected-cycles: A versatile network for parallel computation
SFCS '79 Proceedings of the 20th Annual Symposium on Foundations of Computer Science
Design of Cost-Efficient Interconnect Processing Units: Spidergon STNoC
Design of Cost-Efficient Interconnect Processing Units: Spidergon STNoC
Beyond Fat--tree: Unidirectional Load--Balanced Multistage Interconnection Network
IEEE Computer Architecture Letters
Resource Sharing in Networks-on-Chip of Large Many-core Embedded Systems
ICPPW '09 Proceedings of the 2009 International Conference on Parallel Processing Workshops
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On-chip interconnection networks (OCINs) in many-core embedded systems consume large portions of the chip's area, cost, delay and power. In addition to competing in area, cost, and power, OCINs must feature low diameters to meet real time deadlines. To achieve these goals, designing low-latency networks and sharing network resources are essential. We explore 13 OCINs - some are new such as the Enhanced Kite and the Spidergon-Donut networks - in 64-core systems with various topologies and properties. We also derive and compare their worst case delays, longest and average distances, critical link lengths, bisection bandwidths, total link and router costs, and total arbiter powers. Results indicate that the Enhanced Kite, Kite, Spidergon-Donut and Spidergon-Donut4 stand out in best worst-case delays with the Spidergon-Donut4 additionally featuring lower link and router costs, total arbiter power, and better 2D implementation and scalability.