Computers and Electrical Engineering
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Networks-on-chip in many-core embedded systems consume large portions of the chip’s area, cost, delay and power. In real-time embedded systems meeting the real time targets is critical. Therefore networks-on-chip must provide a communication infrastructure with worst case delays acceptably low to meet the time deadlines. This requirement directly translates into scalable networks with low diameters. Furthermore, with a large number of cores, the cost, area, and power become prime issues. One way to achieve these goals is by sharing system resources such as switches and employing circuit switching. We explore 4 on-chip interconnection networks (OCINs) in 64-core systems with switches shared by cores in core clusters and estimate their worst case latencies with Peh and Dally’s router delay model and published wire delays. For these five OCINs, we also derive their diameters, average delays, switch degrees, and total link costs and compare them to the standard 2D Mesh OCIN. Results indicate that switch sharing by core clusters is effective in reducing the worst case and average communication delays, and the total number of links and switches.