A Delay Model and Speculative Architecture for Pipelined Routers
HPCA '01 Proceedings of the 7th International Symposium on High-Performance Computer Architecture
Low-Latency Virtual-Channel Routers for On-Chip Networks
Proceedings of the 31st annual international symposium on Computer architecture
A Statistical Traffic Model for On-Chip Interconnection Networks
MASCOTS '06 Proceedings of the 14th IEEE International Symposium on Modeling, Analysis, and Simulation
NOCS '10 Proceedings of the 2010 Fourth ACM/IEEE International Symposium on Networks-on-Chip
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Through low-level simulation and analysis, we find that the virtual channel allocator (VA) consumes large area and power while it is not critical in the performances of a NoC. Thus, it is possible to reduce the costs of VA with only a small penalty in network performances. This paper proposes two low-cost VA architectures: look-ahead VA and unfair VA. Compared with a general VA, the look-ahead VA reduces the number of both input VC arbiters and output VC arbiters while the unfair VA decreases the size of the output VC arbiters. Our experiments based on UMC 130 nm SP library show that the two architectures jointly save area cost by 70.95% and power consumption by 76.21% with nearly no adverse effect on network latency and throughput. To the best of our knowledge, it is the first time a VC allocator design is optimized in the context of NoC.