Comparative study of switching techniques for network-on-chip architecture

Authors:
Yogita A. Sadawarte;Mahendra A. Gaikwad;Rajendra M. Patrikar
Affiliations:
Bapurao Deshmukh College of Engineering, Sevagram, Wardha, Maharashtra, India;Bapurao Deshmukh College of Engineering, Sevagram, Wardha, Maharashtra, India;Visvesvaraya National Institute of Technology (VNIT) Nagpur, Maharashtra, India
Venue:
Proceedings of the 2011 International Conference on Communication, Computing & Security
Year:
2011

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Abstract

In Network--on-Chip architecture (NoC) energy consumption is broadly classified as communication energy & computational energy. Communication energy is highly dominant at higher semiconductor technology due to delay in communication channel. Whereas computational energy decreases with recent trends in semiconductor technology. In communication among IP cores power dissipated in switching process is highly dominant, known as dynamic power. In this paper we compare different switching techniques used in Network on chip architecture. In this paper we discuss the optimization of the dynamic power due to switching activity in the Network-on-Chip architecture that is possible by applying switching algorithms. In this paper we study different switching techniques which are used in Network-on-Chip architecture.