Design methods for attaining IBM System z9 processor cycle-time goals

Authors:
G. Mayer;G. Doettling;R. F. Rizzolo;C. J. Berry;S. M. Carey;C. M. Carney;J. Keinert;P. Loeffler;W. Nop;D. E. Skooglund;V. A. Victoria;A. P. Wagstaff;P. M. Williams
Affiliations:
-;-;-;-;-;-;-;-;-;-;-;-;-
Venue:
IBM Journal of Research and Development
Year:
2007

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Abstract

Cycle-time targets were set for the IBM System z9TM processor subsystem prior to building the system, and achieving these targets was one of the biggest challenges we faced during hardware development. In particular, although the processor-subsystem cycle-time improvement was driven primarily by the technology migration from CMOS 9S (130-nm lithography) for the prior IBM System z990 to CMOS IOSO (90-nm lithography) for the new system, the cooling capability for the System z9 resulted from a direct migration of the System z990 implementation with very limited improvements. The higher device current leakage and power associated with the technology migration, combined with the fixed cooling capability, created a technology challenge in which the subsystem cycle time and performance were potentially limited by cooling capability. Our solution emphasized silicon technology development, chip design, and hardware characterization and tuning. Ultimately, the System z9 processor subsystem achieved operation at 1.7 GHz, which exceeded the original target.