First- and second-level packaging of the z990 processor cage
IBM Journal of Research and Development
High-speed interconnect and packaging design of the IBM System z9 processor cage
IBM Journal of Research and Development
Design methods for attaining IBM System z9 processor cycle-time goals
IBM Journal of Research and Development
High-speed interconnect and packaging design of the IBM System z9 processor cage
IBM Journal of Research and Development
IBM System z9 eFUSE applications and methodology
IBM Journal of Research and Development
IBM Journal of Research and Development
Design and verification of the IBM system z10 I/O subsystem chips
IBM Journal of Research and Development
IBM system z10 firmware simulation
IBM Journal of Research and Development
Electronic packaging of the IBM System z196 enterprise-class server processor cage
IBM Journal of Research and Development
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As mainframes evolve and deliver higher performance, technologists are focusing less on processor speed and more on overall system performance to create optimized systems. One important area of focus for performance improvement involves chip-to-chip interconnects, with their associated bandwidths and latencies. IBM and related computer manufacturers are optimizing the characteristics of interconnects between processors as well as between processors and their supporting chip sets (local cache, memory, I/O bridge). This paper describes the IBM proprietary high-speed interface known as Elastic Interface (EI), which is used for nearly all chip-to-chip communication in the IBM System z9TM. In particular, EI is a generic high-speed, source-synchronous interface used to transfer addresses, controls, and data between CPUs, L2 caches, memory subsystems, switches, and I/O hubs. The EI has single-ended data lines, resulting in twice the performance (bandwidth per pin) of similar buses operating with two differential lines per signal.