Coordination of time-of-day clocks among multiple systems
IBM Journal of Research and Development
X-Gen: a random test-case generator for systems and SoCs
HLDVT '02 Proceedings of the Seventh IEEE International High-Level Design Validation and Test Workshop
High-speed source-synchronous interface for the IBM System z9 processor
IBM Journal of Research and Development
Handbook of Fiber Optic Data Communication, Third Edition: A Practical Guide to Optical Networking
Handbook of Fiber Optic Data Communication, Third Edition: A Practical Guide to Optical Networking
Self-timed interface for S/390 I/O subsystem interconnection
IBM Journal of Research and Development
POWER4 system microarchitecture
IBM Journal of Research and Development
Self-timed interface of the input/output subsystem of the IBM eServer z900
IBM Journal of Research and Development
Design and verification of the IBM system z10 I/O subsystem chips
IBM Journal of Research and Development
IBM system z10 open systems adapter ethernet data router
IBM Journal of Research and Development
IBM system z10 processor cache subsystem microarchitecture
IBM Journal of Research and Development
Design and verification of the IBM system z10 I/O subsystem chips
IBM Journal of Research and Development
Packaging design challenges of the IBM system z10 enterprise class server
IBM Journal of Research and Development
IBM system z10 firmware simulation
IBM Journal of Research and Development
Overview of IBM zEnterprise 196 I/O subsystem with focus on new PCI express infrastructure
IBM Journal of Research and Development
IBM Parallel Sysplex design for the IBM z196 system
IBM Journal of Research and Development
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The performance, reliability, and functionality of a large server are greatly influenced by the design characteristics of its I/O subsystem. The critical components of the IBM System z10™ I/O subsystem have, therefore, been significantly improved in terms of performance, capability, and cost. The first-order network has been redesigned from the long-evolved enhanced self-timed interface (eSTI) links to utilize InfiniBand™ links. A redesign of the host logic of I/O chips and the fiberoptic interfaces within the links made it possible to introduce InfiniBand-based IBM Parallel Sysplex® links. A broad range of legacy I/O channels have been carried forward to connect through InfiniBand, and a foundation has been laid for new channel types of improved functionality and performance. The first such hardware channel to be introduced is the next generation of Ethernet-virtualization data routers. A new and methodical recovery structure has been designed to ensure consistent, extensive support of reliability, availability, and serviceability. A building-block-oriented design process has been developed to enable the innovations that made these advances possible. Finally, a new performance verification methodology has been introduced to ensure that the system and subsystem designs are balanced to make effective use of the increased capacity.