First- and second-level packaging of the z990 processor cage

  • Authors:

  • T.-M. Winkel;W. D. Becker;H. Harrer;H. Pross;D. Kaller;B. Garben;B. J. Chamberlin;S. A. Kuppinger

  • Affiliations:

  • IBM Systems and Technology Group, IBM Deutschland Entwicklung GmbH, Schenaicherstrasse 220, 71032 Boeblingen, Germany;IBM Systems and Technology Group, 2455 South Road, Poughkeepsie, New York;IBM Systems and Technology Group, IBM Deutschland Entwicklung GmbH, Schenaicherstrasse 220, 71032 Boeblingen, Germany;IBM Systems and Technology Group, IBM Deutschland Entwicklung GmbH, Schenaicherstrasse 220, 71032 Boeblingen, Germany;IBM Systems and Technology Group, IBM Deutschland Entwicklung GmbH, Schenaicherstrasse 220, 71032 Boeblingen, Germany;IBM Systems and Technology Group, IBM Deutschland Entwicklung GmbH, Schenaicherstrasse 220, 71032 Boeblingen, Germany;IBM Integrated Supply Chain Division, 1701 North Street, Endicott, New York;IBM Systems and Technology Group, 2455 South Road, Poughkeepsie, New York

  • Venue:
  • IBM Journal of Research and Development
  • Year:
  • 2004

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Abstract

In this paper, we describe the challenging first- and second-level packaging technology of a new system packaging architecture for the IBM eServerTM z990. The z990 dramatically increases the volumetric processor density over that of the predecessor z900 by implementing a super-blade design comprising four node cards. Each blade is plugged into a common center board, and a blade contains the node with up to sixteen processor cores on the multichip module (MCM), up to 64 GB of memory on two memory cards, and up to twelve self-timed interface (STI) cables plugged into the front of the node. Each glass-ceramic MCM carries 16 chips dissipating a maximum power of 800 W. In this super-blade design, the packaging complexity is increased dramatically over that of the previous zSeries® eServer z900 to achieve increased volumetric density, processor performance, and system scalability. This approach permits the system to be scaled from one to four nodes, with full interaction between all nodes using a ring structure for the wiring between the four nodes. The processor frequencies are increased to 1.2 GHz, with a 0.6-GHz nest with synchronous double-data-rate interchip and interblade communication. This data rate over these package connections demands an electrical verification methodology that includes all of the different relevant system components to ensure that the proper signal and power distribution operation is achieved. The signal integrity analysis verifies that crosstalk limits are not exceeded and proper timing relationships are maintained. The power integrity simulations are performed to optimize the hierarchical decoupling in order to maintain the voltage on the power distribution networks within prescribed limits.