Shared-cache clusters in a system with a fully shared memory
IBM Journal of Research and Development - Special issue: IBM S/390 G3 and G4
IBM Journal of Research and Development
Processor subsystem interconnect architecture for a large symmetric multiprocessing system
IBM Journal of Research and Development
IBM Journal of Research and Development
IBM system z10 performance improvements with software and hardware synergy
IBM Journal of Research and Development
Hi-index | 0.00 |
The CMOS-based IBM S/390 Parallel Enterprise Servers™ have always employed the technique of memory caching to bridge the gap between processor speed and main-memory access time. However, that gap has widened with each succeeding system generation, requiring increasingly sophisticated, multiple-level cache structures in order to minimize memory-access latency. The IBM S/390® G5 and G6 include two-level caching, with a binodal second-level cache. This paper reviews the principles of cache design, discusses the performance requirements of S/390 relative to caching, and describes how those requirements are addressed by the binodal L2 cache in the G5 and G6 systems.