Techniques for Optimizing Applications: High Performance Computing
Techniques for Optimizing Applications: High Performance Computing
zAAPs and zIIPs: increasing the strategic value of System z
IBM Journal of Research and Development
IBM S/390 storage hierarchy: G5 and G6 performance considerations
IBM Journal of Research and Development
IBM system z10 processor cache subsystem microarchitecture
IBM Journal of Research and Development
Design and microarchitecture of the IBM system z10 microprocessor
IBM Journal of Research and Development
Mining opportunities for code improvement in a just-in-time compiler
CC'10/ETAPS'10 Proceedings of the 19th joint European conference on Theory and Practice of Software, international conference on Compiler Construction
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This paper describes efforts to more fully exploit the synergy potential between hardware and software to improve performance on the IBM System z® platform. Although the IBM commitment to upward compatibility for System z mainframes prevents us from engaging in hardware generational tuning, software stack improvements aimed at one generation of hardware tend to increase in value for subsequent generations. This paper presents some of the software synergy efforts that were made to complement hardware design characteristics to improve performance and that will continue to be of benefit in future machine generations. Also presented is IBM z/OS® HiperDispatch management, which minimizes cache coherency penalties when dispatching work, and the new IBM System z10™ hardware instrumentation, the central processor measurement facility (CPMF), which supports software performance optimizations by providing counters and sampling and allowing the software to measure central processor activities to determine hotspots. The CPMF is nondisruptive, has low overhead, and can run in multiple logical partitions simultaneously.