Transactional memory: architectural support for lock-free data structures
ISCA '93 Proceedings of the 20th annual international symposium on computer architecture
Speculative lock elision: enabling highly concurrent multithreaded execution
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Software transactional memory: why is it only a research toy?
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Hybrid NOrec: a case study in the effectiveness of best effort hardware transactional memory
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Evaluation of Blue Gene/Q hardware support for transactional memories
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Transactional Memory Architecture and Implementation for IBM System Z
MICRO-45 Proceedings of the 2012 45th Annual IEEE/ACM International Symposium on Microarchitecture
The balancing act of choosing nonblocking features
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SC '13 Proceedings of the International Conference on High Performance Computing, Networking, Storage and Analysis
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Lock elision enables existing lock-based programs to achieve the performance benefits of nonblocking synchronization and fine-grain locking with minor software engineering effort.