Reasoning about parallel architectures
Reasoning about parallel architectures
Transactional memory: architectural support for lock-free data structures
ISCA '93 Proceedings of the 20th annual international symposium on computer architecture
rePLay: A Hardware Framework for Dynamic Optimization
IEEE Transactions on Computers
Speculative lock elision: enabling highly concurrent multithreaded execution
Proceedings of the 34th annual ACM/IEEE international symposium on Microarchitecture
Transactional Memory Coherence and Consistency
Proceedings of the 31st annual international symposium on Computer architecture
Virtualizing Transactional Memory
Proceedings of the 32nd annual international symposium on Computer Architecture
Exceptions and side-effects in atomic blocks
Science of Computer Programming - Special issue: Concurrency and synchronization in Java programs
Architectural Semantics for Practical Transactional Memory
Proceedings of the 33rd annual international symposium on Computer Architecture
Supporting nested transactional memory in logTM
Proceedings of the 12th international conference on Architectural support for programming languages and operating systems
Tradeoffs in transactional memory virtualization
Proceedings of the 12th international conference on Architectural support for programming languages and operating systems
Hardware atomicity for reliable software speculation
Proceedings of the 34th annual international symposium on Computer architecture
Subtleties of Transactional Memory Atomicity Semantics
IEEE Computer Architecture Letters
Speculative optimization using hardware-monitored guarded regions for java virtual machines
Proceedings of the 3rd international conference on Virtual execution environments
Foundations of the C++ concurrency memory model
Proceedings of the 2008 ACM SIGPLAN conference on Programming language design and implementation
Early experience with a commercial hardware transactional memory implementation
Proceedings of the 14th international conference on Architectural support for programming languages and operating systems
An Analysis of I/O And Syscalls In Critical Sections And Their Implications For Transactional Memory
ISPASS '08 Proceedings of the ISPASS 2008 - IEEE International Symposium on Performance Analysis of Systems and software
Lock elision for read-only critical sections in Java
PLDI '10 Proceedings of the 2010 ACM SIGPLAN conference on Programming language design and implementation
Understanding POWER multiprocessors
Proceedings of the 32nd ACM SIGPLAN conference on Programming language design and implementation
Proceedings of the 33rd ACM SIGPLAN conference on Programming Language Design and Implementation
Transactional Memory Architecture and Implementation for IBM System Z
MICRO-45 Proceedings of the 2012 45th Annual IEEE/ACM International Symposium on Microarchitecture
The balancing act of choosing nonblocking features
Communications of the ACM
The Balancing Act of Choosing Nonblocking Features
Queue - Development
SI-TM: reducing transactional memory abort rates through snapshot isolation
Proceedings of the 19th international conference on Architectural support for programming languages and operating systems
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On the twentieth anniversary of the original publication [10], following ten years of intense activity in the research literature, hardware support for transactional memory (TM) has finally become a commercial reality, with HTM-enabled chips currently or soon-to-be available from many hardware vendors. In this paper we describe architectural support for TM added to a future version of the Power ISA™. Two imperatives drove the development: the desire to complement our weakly-consistent memory model with a more friendly interface to simplify the development and porting of multithreaded applications, and the need for robustness beyond that of some early implementations. In the process of commercializing the feature, we had to resolve some previously unexplored interactions between TM and existing features of the ISA, for example translation shootdown, interrupt handling, atomic read-modify-write primitives, and our weakly consistent memory model. We describe these interactions, the overall architecture, and discuss the motivation and rationale for our choices of architectural semantics, beyond what is typically found in reference manuals.