Contention-aware scheduler: unlocking execution parallelism in multithreaded java programs
Proceedings of the 23rd ACM SIGPLAN conference on Object-oriented programming systems languages and applications
What the parallel-processing community has (failed) to offer the multi/many-core generation
Journal of Parallel and Distributed Computing
On the energy-efficiency of software transactional memory
Proceedings of the 22nd Annual Symposium on Integrated Circuits and System Design: Chip on the Dunes
Implementing Fine/Medium Grained TLP Support in a Many-Core Architecture
SAMOS '09 Proceedings of the 9th International Workshop on Embedded Computer Systems: Architectures, Modeling, and Simulation
Software Transactional Memories: An Approach for Multicore Programming
PaCT '09 Proceedings of the 10th International Conference on Parallel Computing Technologies
Concurrent programming with revisions and isolation types
Proceedings of the ACM international conference on Object oriented programming systems languages and applications
Semantics of concurrent revisions
ESOP'11/ETAPS'11 Proceedings of the 20th European conference on Programming languages and systems: part of the joint European conferences on theory and practice of software
Software transactional memories: an approach for multicore programming
The Journal of Supercomputing
Read invisibility, virtual world consistency and probabilistic permissiveness are compatible
ICA3PP'11 Proceedings of the 11th international conference on Algorithms and architectures for parallel processing - Volume Part I
SIROCCO'09 Proceedings of the 16th international conference on Structural Information and Communication Complexity
Efficient transaction nesting in hardware transactional memory
ARCS'10 Proceedings of the 23rd international conference on Architecture of Computing Systems
Theoretical Computer Science
Transactional Memory Architecture and Implementation for IBM System Z
MICRO-45 Proceedings of the 2012 45th Annual IEEE/ACM International Symposium on Microarchitecture
FaulTM: error detection and recovery using hardware transactional memory
Proceedings of the Conference on Design, Automation and Test in Europe
Towards a universal construction for transaction-based multiprocess programs
Theoretical Computer Science
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Writing applications that benefit from the massive computational power of future multicore chip multiprocessors will not be an easy task for mainstream programmers accustomed to sequential algorithms rather than parallel ones. This article presents a survey of transactional memory, a mechanism that promises to enable scalable performance while freeing programmers from some of the burden of modifying their parallel code.