Transactional memory: architectural support for lock-free data structures
ISCA '93 Proceedings of the 20th annual international symposium on computer architecture
Proceedings of the fourteenth annual ACM symposium on Principles of distributed computing
Lock-free linked lists using compare-and-swap
Proceedings of the fourteenth annual ACM symposium on Principles of distributed computing
Concurrent programming in ERLANG (2nd ed.)
Concurrent programming in ERLANG (2nd ed.)
Communicating sequential processes
Communications of the ACM
Speculative lock elision: enabling highly concurrent multithreaded execution
Proceedings of the 34th annual ACM/IEEE international symposium on Microarchitecture
StreamIt: A Language for Streaming Applications
CC '02 Proceedings of the 11th International Conference on Compiler Construction
Language support for lightweight transactions
OOPSLA '03 Proceedings of the 18th annual ACM SIGPLAN conference on Object-oriented programing, systems, languages, and applications
DCAS is not a silver bullet for nonblocking algorithm design
Proceedings of the sixteenth annual ACM symposium on Parallelism in algorithms and architectures
Brief announcement: implementing multi-word atomic snapshots on current hardware
Proceedings of the twenty-third annual ACM symposium on Principles of distributed computing
Virtualizing Transactional Memory
Proceedings of the 32nd annual international symposium on Computer Architecture
Proceedings of the eleventh ACM SIGPLAN symposium on Principles and practice of parallel programming
Proceedings of the 12th international conference on Architectural support for programming languages and operating systems
Architectural Support for Software Transactional Memory
Proceedings of the 39th Annual IEEE/ACM International Symposium on Microarchitecture
Understanding Tradeoffs in Software Transactional Memory
Proceedings of the International Symposium on Code Generation and Optimization
Dynamic filtering: multi-purpose architecture support for language runtime systems
Proceedings of the fifteenth edition of ASPLOS on Architectural support for programming languages and operating systems
| Hi-index | 0.00 |
Just One Lousy Bit! I want to know if any memory operation misses or any line in my L1 cache gets evicted. Why? Because with this one Bit I can write any number of lock-free algorithms easily. This Bit gives me an N-word atomic read set, and with a typical Store Conditional instruction a 1-word atomic write set. The algorithm writing community has begged for D-CAS or Hardware Transactional Memory for years, but proposals far outstrip implementations: neither are available on any commodity system. With this Bit I hope to lower the hardware costs as low as possible while still being useful.