SAMOS '08 Proceedings of the 8th international workshop on Embedded Computer Systems: Architectures, Modeling, and Simulation
IPC Control for Multiple Real-Time Threads on an In-Order SMT Processor
HiPEAC '09 Proceedings of the 4th International Conference on High Performance Embedded Architectures and Compilers
Fixed-priority scheduling on prioritized SMT processor
PDCS '07 Proceedings of the 19th IASTED International Conference on Parallel and Distributed Computing and Systems
Soft real-time scheduling with tardiness bounds on prioritized SMT processors
PDCN '08 Proceedings of the IASTED International Conference on Parallel and Distributed Computing and Networks
How to enhance a superscalar processor to provide hard real-time capable in-order SMT
ARCS'10 Proceedings of the 23rd international conference on Architecture of Computing Systems
ACM SIGBED Review - Special Issue on the 24th Euromicro Conference on Real-Time Systems
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This paper describes a novel processor architecture, the prioritized SMT architecture with the IPC control method, to guarantee the execution time of real-time threads. Based on priority set by a real-time scheduler, all hardware resources including cache systems, fetch, issue, and execution units, are controlled, so that our processor can execute multiple threads in real-time. All runnable threads are simultaneously executed as much as possible in priority order, so that the execution order becomes congruent with the priority order set by a real-time scheduler. If a resource conflict occurs, the lower priority threads are kept waiting until the higher priority thread finishes using the resource. In brief, context switching required for real-time scheduling and execution is converted to the prioritized SMT execution. Here, some triggers including cache misses and branch prediction misses fluctuate the execution speed of a thread. Additionally, in case of an SMT processor, the execution time of each thread may vary according to a combination of simultaneous executing threads. To guarantee the execution time of realtime threads accurately, the IPC control method that monitors and controls each thread IPC in a feedback loop is designed and implemented. Our IPC control method can keep the IPC deviation of the thread within ..1% bounds, if the target IPC is less than 80% of the single thread execution IPC. Our processor is implemented as a processing core of a system LSI, which process was TSMC 0.13um 8 layered Cu wiring, used for distributed real-time systems including humanoid robots, bilateral robots, embedded control systems, and ubiquitous computing systems.