Energy-Efficient Simultaneous Thread Fetch from Different Cache Levels in a Soft Real-Time SMT Processor

Authors:
Emre Özer;Ronald G. Dreslinski;Trevor Mudge;Stuart Biles;Krisztián Flautner
Affiliations:
ARM Ltd., Cambridge, UK;Department of Electrical Engineering and Computer Science, University of Michigan, Ann Arbor, US;Department of Electrical Engineering and Computer Science, University of Michigan, Ann Arbor, US;ARM Ltd., Cambridge, UK;ARM Ltd., Cambridge, UK
Venue:
SAMOS '08 Proceedings of the 8th international workshop on Embedded Computer Systems: Architectures, Modeling, and Simulation
Year:
2008

Citing 11
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Abstract

This paper focuses on the instruction fetch resources in a real-time SMT processor to provide an energy-efficient configuration for a soft real-time application running as a high priority thread as fast as possible while still offering decent progress in low priority or non-real-time thread(s). We propose a fetch mechanism, Fetch-around, where a high priority thread accesses the L1 ICache, and low priority threads directly access the L2. This allows both the high and low priority threads to simultaneously fetch instructions, while preventing the low priority threads from thrashing the high priority thread's ICache data. Overall, we show an energy-performance metric that is 13% better than the next best policy when the high performance thread priority is 10x that of the low performance thread.