Dynamic management of scratch-pad memory space
Proceedings of the 38th annual Design Automation Conference
Compiler-directed scratch pad memory hierarchy design and management
Proceedings of the 39th annual Design Automation Conference
A Loop Transformation Theory and an Algorithm to Maximize Parallelism
IEEE Transactions on Parallel and Distributed Systems
Scratchpad memory: design alternative for cache on-chip memory in embedded systems
Proceedings of the tenth international symposium on Hardware/software codesign
Assigning Program and Data Objects to Scratchpad for Energy Reduction
Proceedings of the conference on Design, automation and test in Europe
Compiler-decided dynamic memory allocation for scratch-pad based embedded systems
Proceedings of the 2003 international conference on Compilers, architecture and synthesis for embedded systems
Data Reuse Analysis Technique for Software-Controlled Memory Hierarchies
Proceedings of the conference on Design, automation and test in Europe - Volume 1
Control Flow Driven Splitting of Loop Nests at the Source Code Level
DATE '03 Proceedings of the conference on Design, Automation and Test in Europe - Volume 1
Layer Assignment echniques for Low Energy in Multi-Layered Memory Organisations
DATE '03 Proceedings of the conference on Design, Automation and Test in Europe - Volume 1
FORAY-GEN: Automatic Generation of Affine Functions for Memory Optimizations
Proceedings of the conference on Design, Automation and Test in Europe - Volume 2
Data partitioning for maximal scratchpad usage
ASP-DAC '03 Proceedings of the 2003 Asia and South Pacific Design Automation Conference
MiBench: A free, commercially representative embedded benchmark suite
WWC '01 Proceedings of the Workload Characterization, 2001. WWC-4. 2001 IEEE International Workshop
Multiprocessor system-on-chip data reuse analysis for exploring customized memory hierarchies
Proceedings of the 43rd annual Design Automation Conference
CODES+ISSS '06 Proceedings of the 4th international conference on Hardware/software codesign and system synthesis
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With the technology advances it becomes feasible to implement a large multiprocessor system on a single chip. In such Systems-on-Chip (SoCs), a significant portion of energy is spent in the memory subsystem. There are several approaches reducing this energy, including the ones at physical, architecture and algorithmic levels. Classical approaches, including algorithmic and some architectural approaches, use static analysis and transformation of the application source code. However, often it is not possible to perform static analysis and optimization of a program's memory access behavior unless the program is written in an easily analyzable form, e.g., free from pointer arithmetic. In this paper, we introduce the FORAY model of a program that allows aggressive analysis of the application's memory behavior and enables such optimizations on arbitrary code which are not possible to apply otherwise. We then present FORAY-GEN: an automated profile-based approach for extraction of the FORAY model from the original program. We also outline our approach in applying FORAY-GEN for multiprocessor SoCs. We demonstrate how FORAY-GEN enhances applicability of other memory subsystem optimization approaches, resulting in an average of two times increase in the number of memory references that can be analyzed by existing static approaches.