Compiler driven data layout optimization for regular/irregular array access patterns

Authors:
Doosan Cho;Sudeep Pasricha;Ilya Issenin;Nikil Dutt;Yunheung Paek;SunJun Ko
Affiliations:
EECS/Seoul National University, Seoul, South Korea;ICS/Univ. of California Irvine, Irvine, USA;ICS/Univ. of California Irvine, Irvine, USA;ICS/Univ. of California Irvine, Irvine, USA;EECS/Seoul National University, Seoul, South Korea;Samsung, Suwon, South Korea
Venue:
Proceedings of the 2008 ACM SIGPLAN-SIGBED conference on Languages, compilers, and tools for embedded systems
Year:
2008

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Abstract

Embedded multimedia applications consist of regular and irregular memory access patterns. Particularly, irregular pattern are not amenable to static analysis for extraction of access patterns, and thus prevent efficient use of a Scratch Pad Memory (SPM) hierarchy for performance and energy improvements. To resolve this, we present a compiler strategy to optimize data layout in regular/irregular multimedia applications running on embedded multiprocessor environments. The goal is to maximize the amount of accesses to the SPM over the entire system which leads to a reduction in the energy consumption of the system. This is achieved by optimizing data placement of application-wide reused data so that it resides in the SPMs of processing elements. Specifically, our scheme is based on a profiling that generates a memory access footprint. The memory access footprint is used to identify data elements with fine granularity that can profitably be placed in the SPMs to maximize performance and energy gains. We present a heuristic approach that efficiently exploits the SPMs using memory access footprint. Our experimental results show that our approach is able to reduce energy consumption by 30% and improve performance by 18% over cache based memory subsystems for various multimedia applications.