Software controlled memory layout reorganization for irregular array access patterns

  • Authors:
  • Doosan Cho;Ilya Issenin;Nikil Dutt;Jonghee W. Yoon;Yunheung Paek

  • Affiliations:
  • Seoul National University;University of California: Irvine;University of California: Irvine;Seoul National University;Seoul National University

  • Venue:
  • CASES '07 Proceedings of the 2007 international conference on Compilers, architecture, and synthesis for embedded systems
  • Year:
  • 2007

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Abstract

Many embedded array-intensive applications have irregular access patterns that are not amenable to static analysis for extraction of access patterns, and thus prevent efficient use of a Scratch Pad Memory (SPM) hierarchy for performance and power improvement. We present a profiling based strategy that generates a memory access trace which can be used to identify data elements with fine granularity that can profitably be placed in the SPMs to maximize performance and energy gains. We developed an entire toolchain that allows incorporation of the code required to profitably move data to SPMs; visualization of the extracted access pattern after profiling; and evaluation/exploration of the generated application code to steer mapping of data to the SPM to yield performance and energy benefits.We present a heuristic approach that efficiently exploits the SPM using the profiler-driven access pattern behaviors. Experimental results on EEMBC and other industrial codes obtained with our framework show that we are able to achieve 36% energy reduction and reduce execution time by up to 22% compared to a cache based system.