Systematic Address and Control Code Transformations for Performance Optimisation of a MPEG-4 Video Decoder

Authors:
M. Palkovic;M. Miranda;K. Denolf;P. Vos;F. Catthoor
Affiliations:
IMEC, Kapeldreef 75, 3001Leuv en, Belgium.;IMEC, Kapeldreef 75, 3001Leuv en, Belgium.;IMEC, Kapeldreef 75, 3001Leuv en, Belgium.;IMEC, Kapeldreef 75, 3001Leuv en, Belgium.;IMEC, Kapeldreef 75, 3001Leuv en, Belgium and also Professor at Katholieke Univ. Leuven
Venue:
ASP-DAC '02 Proceedings of the 2002 Asia and South Pacific Design Automation Conference
Year:
2002

Citing 11
Cited 3

Compilers: principles, techniques, and tools

Compilers: principles, techniques, and tools
Address calculation for retargetable compilation and exploration of instruction-set architectures

DAC '96 Proceedings of the 33rd annual Design Automation Conference
Algorithms for address assignment in DSP code generation

Proceedings of the 1996 IEEE/ACM international conference on Computer-aided design
Analysis and evaluation of address arithmetic capabilities in custom DSP architectures

DAC '97 Proceedings of the 34th annual Design Automation Conference
DSP address optimization using a minimum cost circulation technique

ICCAD '97 Proceedings of the 1997 IEEE/ACM international conference on Computer-aided design
The MPEG-4 Multimedia Coding Standard: Algorithms, Architectures and Applications

Journal of VLSI Signal Processing Systems - Special issue on implementation of MPEG-4 multimedia codecs
Analysis of high-level address code transformations for programmable processors

DATE '00 Proceedings of the conference on Design, automation and test in Europe
Address code generation for digital signal processors

Proceedings of the 38th annual Design Automation Conference
Applying and Implementing the MPEG-4 Multimedia Standard

IEEE Micro
On Speed Optimization of MPEG-4 Decoder for Real-Time Multimedia Applications

ICCIMA '99 Proceedings of the 3rd International Conference on Computational Intelligence and Multimedia Applications
MPEG-4 Video Decoder Optimization

ICMCS '99 Proceedings of the IEEE International Conference on Multimedia Computing and Systems - Volume 2

Software controlled memory layout reorganization for irregular array access patterns

CASES '07 Proceedings of the 2007 international conference on Compilers, architecture, and synthesis for embedded systems
Address Generation Optimization for Embedded High-Performance Processors: A Survey

Journal of Signal Processing Systems
Systematic architecture exploration based on optimistic cycle estimation for low energy embedded processors

Proceedings of the 2009 Asia and South Pacific Design Automation Conference

Quantified Score

Hi-index	0.00

Visualization

Abstract

A cost-efficient realisation of an advanced multimedia system requires high-level memory optimisations to deal with the dominant memory cost. This typically results in more efficient code for both power and system bus load. However, also significant performance improvement can be achieved when carefully optimising the address functionality. This paper shows how the nature of this addressing code and the related control flow allows to transform the complex index, iterator and condition expressions into efficient arithmetic. We apply our ADdress OPTimisation (ADOPT) design technology to low power memory optimised MPEG-4 decoder. When mapped on popular programmable multi-media processor architectures, we obtain factor of 2 in performance gain.