Address assignment combined with scheduling in DSP code generation

  • Authors:
  • Yoonseo Choi;Taewhan Kim

  • Affiliations:
  • Korea Advanced Institute of Science and Technology, Korea;Korea Advanced Institute of Science and Technology, Korea

  • Venue:
  • Proceedings of the 39th annual Design Automation Conference
  • Year:
  • 2002

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Abstract

One of the important issues in embedded system design is to optimize program code for the microprocessor to be stored in ROM. In this paper, we propose an integrated approach to the DSP address code generation problem for minimizing the number of addressing instructions. Unlike previous works in which code scheduling and offset assignment are performed sequentially without any interaction between them, our work tightly couples offset assignment problem with code scheduling to exploit scheduling on minimizing addressing instructions more effectively. We accomplish this by developing a fast but accurate two-phase procedure which, for a sequence of code schedules, finds a sequence of memory layouts with minimum addressing instructions. Experimental results with benchmark DSP programs show improvements of 13%--33% in the address code size over Solve-SOA/GOA [7].