Efficient building block based RTL code generation from synchronous data flow graphs

Authors:
Jens Horstmannshoff;Heinrich Meyr
Affiliations:
Integrated Signal Processing Systems, RWTH Aachen, Germany;Integrated Signal Processing Systems, RWTH Aachen, Germany
Venue:
Proceedings of the 37th Annual Design Automation Conference
Year:
2000

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Abstract

This paper presents a RTL-HDL code generation from synchronous data-flow graphs which supports the building block based design of data-flow oriented ASIC systems. Here, additional interfacing and controlling hardware is generated to adapt non-matching interfacing properties. In order to reduce interface register cost, a retiming approach is taken to schedule optimum building block activation times. The code generation methodology is compared to an existing approach using different case studies.