Graphs and algorithms
Static scheduling of synchronous data flow programs for digital signal processing
IEEE Transactions on Computers
Blocking in a system on a chip
IEEE Spectrum
Software Synthesis from Dataflow Graphs
Software Synthesis from Dataflow Graphs
Efficient building block based RTL code generation from synchronous data flow graphs
Proceedings of the 37th Annual Design Automation Conference
Efficient hardware controller synthesis for synchronous dataflow graph in system level design
ISSS '00 Proceedings of the 13th international symposium on System synthesis
The Implementation of Synchronous Dataflow Graphs Using Reconfigurable Hardware
FPL '00 Proceedings of the The Roadmap to Reconfigurable Computing, 10th International Workshop on Field-Programmable Logic and Applications
Optimized System Synthesis of Complex RT Level Building Blocks from Multirate Dataflow Graphs
Proceedings of the 12th international symposium on System synthesis
Hardware synthesis from coarse-grained dataflow specification for fast HW/SW cosynthesis
Proceedings of the 2nd IEEE/ACM/IFIP international conference on Hardware/software codesign and system synthesis
Dataflow-based mapping of computer vision algorithms onto FPGAs
EURASIP Journal on Embedded Systems
Master Interface for On-chip Hardware Accelerator Burst Communications
Journal of VLSI Signal Processing Systems
Optimized RTL Code Generation from Coarse-Grain Dataflow Specification for Fast HW/SW Cosynthesis
Journal of Signal Processing Systems
Mathematical formalisms for performance evaluation of networks-on-chip
ACM Computing Surveys (CSUR)
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The design of digital signal processing systems typically consists of an algorithm development phase carried out at a behavioral level and the selection of an efficient hardware architecture for implementation. In order to speed up the joint optimization of algorithms and architectures, a fast path to implementation must be provided. This can be achieved efficiently by directly mapping the data flow specification of the system to an RTL target architecture by means of HDL code generation. For algorithm design, communication systems are most easily modeled using multirate data flow graphs in which no notion of time is maintained. HDL code generation introduces a cycle based timing model and maps the data flow models to RTL implementations, which are usually taken from a library. Due to the increase in ASIC design complexity, these building blocks reach a high level of functionality and have complex interfacing properties. Therefore, it becomes necessary to generate additional interfacing and controlling hardware to synthesize an operable system. In this paper, we present a new approach of mapping multirate dataflow graphs to complex RTL hardware models and derive algorithms to synthesize these high-level RTL building blocks into a complete operable system.