Dataflow-based mapping of computer vision algorithms onto FPGAs

  • Authors:

  • Mainak Sen;Ivan Corretjer;Fiorella Haim;Sankalita Saha;Jason Schlessman;Tiehan Lv;Shuvra S. Bhattacharyya;Wayne Wolf

  • Affiliations:

  • Department of Electrical and Computer Engineering, University of Maryland, College Park, MD;Department of Electrical and Computer Engineering, University of Maryland, College Park, MD;Department of Electrical and Computer Engineering, University of Maryland, College Park, MD;Department of Electrical and Computer Engineering, University of Maryland, College Park, MD;Department of Electrical Engineering, Princeton University, Princeton, NJ;Department of Electrical Engineering, Princeton University, Princeton, NJ;Department of Electrical and Computer Engineering, University of Maryland, College Park, MD;Department of Electrical Engineering, Princeton University, Princeton, NJ

  • Venue:
  • EURASIP Journal on Embedded Systems
  • Year:
  • 2007

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Abstract

We develop a design methodology for mapping computer vision algorithms onto an FPGA through the use of coarse-grain reconfigurable dataflow graphs as a representation to guide the designer. We first describe a new dataflow modeling technique called homogeneous parameterized dataflow (HPDF), which effectively captures the structure of an important class of computer vision applications. This form of dynamic dataflow takes advantage of the property that in a large number of image processing applications, data production and consumption rates can vary, but are equal across dataflow graph edges for any particular application iteration. After motivating and defining the HPDF model of computation, we develop an HPDF-based design methodology that offers useful properties in terms of verifying correctness and exposing performance-enhancing transformations; we discuss and address various challenges in efficiently mapping an HPDF-based application representation into target-specific HDL code; and we present experimental results pertaining to the mapping of a gesture recognition application onto the Xilinx Virtex II FPGA.