Statecharts: A visual formalism for complex systems
Science of Computer Programming
Multiprocessor scheduling to account for interprocessor communication
Multiprocessor scheduling to account for interprocessor communication
Compile-time scheduling of dataflow program graphs with dynamic constructs
Compile-time scheduling of dataflow program graphs with dynamic constructs
Fast Prototyping of Datapath-Intensive Architectures
IEEE Design & Test
A Hardware-Software Codesign Methodology for DSP Applications
IEEE Design & Test
Consistency in Dataflow Graphs
IEEE Transactions on Parallel and Distributed Systems
Generating Compact Code From Dataflow Specifications of
Generating Compact Code From Dataflow Specifications of
Scheduling dynamic dataflow graphs with bounded memory using the token flow model
Scheduling dynamic dataflow graphs with bounded memory using the token flow model
Synthesis of multi-rate and variable rate circuits for high speed telecommunications applications
EDTC '97 Proceedings of the 1997 European conference on Design and Test
Dataflow-based mapping of computer vision algorithms onto FPGAs
EURASIP Journal on Embedded Systems
Worst-case throughput analysis of real-time dynamic streaming applications
Proceedings of the eighth IEEE/ACM/IFIP international conference on Hardware/software codesign and system synthesis
Mathematical formalisms for performance evaluation of networks-on-chip
ACM Computing Surveys (CSUR)
Analysis of multi-domain scenarios for optimized dynamic power management strategies
DATE '12 Proceedings of the Conference on Design, Automation and Test in Europe
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This paper presents an analytical model for the behavior of dataflow graphs with data-dependent control flow and discusses its suitability to the generation of efficient software and hardware implementations of digital signal processing (DSP) applications. In the model, the number of tokens produced or consumed by each actor is given as a symbolic function of the Boolean values in the system; in addition, it may vary cyclically to permit more memory-efficient multirate implementations. The model can be used to extend the ability of block-diagram-oriented systems for DSP design, such as Ptolemy [1], to produce efficient hardware and software implementations; this permits the hardware-software codesign techniques of [2] to be efficiently targeted at a wider class of problems, those involving some asynchronous behavior, for example.