Digital receiver design using VHDL generation from data flow graphs
DAC '95 Proceedings of the 32nd annual ACM/IEEE Design Automation Conference
CAD challenges in multimedia computing
ICCAD '95 Proceedings of the 1995 IEEE/ACM international conference on Computer-aided design
Extended Synchronous Dataflow for Efficient DSP System Prototyping
RSP '99 Proceedings of the Tenth IEEE International Workshop on Rapid System Prototyping
Optimized System Synthesis of Complex RT Level Building Blocks from Multirate Dataflow Graphs
Proceedings of the 12th international symposium on System synthesis
IEEE Transactions on Signal Processing
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Even though high-level hardware synthesis from dataflow graphs becomes popular in designing DSP systems, currently used dataflow models are inefficient to deal with emerging multimedia applications since they do not support global parameter update.In this paper, we propose a VHDL code generation method from synchronous piggybacked dataflow (SPDF) which is an extension of synchronous dataflow (SDF) for representing multimedia applications. Through constructing globally shared memory structure with limited access, we can obtain an efficient RTL architecture in terms of memory and performance compared with other approaches. We demonstrate the usefulness of the proposed approach using a preliminary example of MP3 decoders.