Static scheduling of synchronous data flow programs for digital signal processing
IEEE Transactions on Computers
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IEEE Transactions on Software Engineering - Special issue on formal methods in software practice
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CAV '02 Proceedings of the 14th International Conference on Computer Aided Verification
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Memory Management for Synthesis of DSP Software
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ACM Transactions on Design Automation of Electronic Systems (TODAES)
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DATE '12 Proceedings of the Conference on Design, Automation and Test in Europe
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Image Communication
Journal of Real-Time Image Processing
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Synchronous Dataflow (SDF) is a widely-used model of computation for digital signal processing and multimedia applications, which are typically implemented on memory constrained hardware platforms. SDF can be statically analyzed and scheduled, and the memory requirement for correct execution can be predicted at compile time. In this paper, we present an efficient technique based on model-checking for exact analysis of minimal buffer requirement of an SDF graph to guarantee deadlock-free execution. Performance evaluation shows that our approach can achieve significant performance improvements compared to related work.