Static scheduling of synchronous data flow programs for digital signal processing
IEEE Transactions on Computers
Approximation algorithms for scheduling unrelated parallel machines
Mathematical Programming: Series A and B
Parallel program performance metrics: a comprison and validation
Proceedings of the 1992 ACM/IEEE conference on Supercomputing
Bounded scheduling of process networks
Bounded scheduling of process networks
Static scheduling algorithms for allocating directed task graphs to multiprocessors
ACM Computing Surveys (CSUR)
First version of a data flow procedure language
Programming Symposium, Proceedings Colloque sur la Programmation
Convex Optimization
Proceedings of the 42nd annual Design Automation Conference
The 42nd Annual Design Automation Conference 2005
Memory Management for Synthesis of DSP Software
Memory Management for Synthesis of DSP Software
Static Scheduling and Software Synthesis for Dataflow Graphs with Symbolic Model-Checking
RTSS '07 Proceedings of the 28th IEEE International Real-Time Systems Symposium
CODES+ISSS '09 Proceedings of the 7th IEEE/ACM international conference on Hardware/software codesign and system synthesis
Software Code Generation for the RVC-CAL Language
Journal of Signal Processing Systems
Synthesizing Hardware from Dataflow Programs
Journal of Signal Processing Systems
IEEE Transactions on Circuits and Systems for Video Technology
Secure computing with the MPEG RVC framework
Image Communication
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The recent MPEG Reconfigurable Media Coding (RMC) standard aims at defining media processing specifications (e.g. video codecs) in a form that abstracts from the implementation platform, but at the same time is an appropriate starting point for implementation on specific targets. To this end, the RMC framework has standardized both an asynchronous dataflow model of computation and an associated specification language. Either are providing the formalism and the theoretical foundation for multimedia specifications. Even though these specifications are abstract and platform-independent the new approach of developing implementations from such initial specifications presents obvious advantages over the approaches based on classical sequential specifications. The advantages appear particularly appealing when targeting the current and emerging homogeneous and heterogeneous manycore or multicore processing platforms. These highly parallel computing machines are gradually replacing single-core processors, particularly when the system design aims at reducing power dissipation or at increasing throughput. However, a straightforward mapping of an abstract dataflow specification onto a concurrent and heterogeneous platform does often not produce an efficient result. Before an abstract specification can be translated into an efficient implementation in software and hardware, the dataflow networks need to be partitioned and then mapped to individual processing elements. Moreover, system performance requirements need to be accounted for in the design optimization process. This paper discusses the state of the art of the combinatorial problems that need to be faced at this design space exploration step. Some recent developments and experimental results for image and video coding applications are illustrated. Both well-known and novel heuristics for problems such as mapping, scheduling and buffer minimization are investigated in the specific context of exploring the design space of dataflow program implementations.