Joint Minimization of Code and Data for Synchronous DataflowPrograms
Formal Methods in System Design
Memory efficient software synthesis form dataflow graph
Proceedings of the 11th international symposium on System synthesis
Memory efficient software synthesis with mixed coding style from dataflow graphs
IEEE Transactions on Very Large Scale Integration (VLSI) Systems - Special issue on the 11th international symposium on system-level synthesis and design (ISSS'98)
Communications of the ACM
Efficient code synthesis from extended dataflow graphs for multimedia applications
Proceedings of the 39th annual Design Automation Conference
Software Synthesis from Dataflow Graphs
Software Synthesis from Dataflow Graphs
Synthesis of Embedded Software from Synchronous Dataflow Specifications
Journal of VLSI Signal Processing Systems
Buffer Memory Optimization in DSP Applications - An Evolutionary Approach
PPSN V Proceedings of the 5th International Conference on Parallel Problem Solving from Nature
Managing Memory Requirements in the Synthesis of Real-Time Systems from Processing Graphs
RTAS '98 Proceedings of the Fourth IEEE Real-Time Technology and Applications Symposium
Coordination-centric debugging for heterogeneous distributed embedded systems
Coordination-centric debugging for heterogeneous distributed embedded systems
Fractional Rate Dataflow Model for Efficient Code Synthesis
Journal of VLSI Signal Processing Systems
ACM Transactions on Design Automation of Electronic Systems (TODAES)
Minimising buffer requirements of synchronous dataflow graphs with model checking
Proceedings of the 42nd annual Design Automation Conference
Shift buffering technique for automatic code synthesis from synchronous dataflow graphs
CODES+ISSS '05 Proceedings of the 3rd IEEE/ACM/IFIP international conference on Hardware/software codesign and system synthesis
Eco: Ultra-Wearable and Expandable Wireless Sensor Platform
BSN '06 Proceedings of the International Workshop on Wearable and Implantable Body Sensor Networks
Beyond single-appearance schedules: Efficient DSP software synthesis using nested procedure calls
ACM Transactions on Embedded Computing Systems (TECS) - SPECIAL ISSUE SCOPES 2005
Proceedings of the 2009 Asia and South Pacific Design Automation Conference
Scheduling optimisations for SPIN to minimise buffer requirements in synchronous data flow
Proceedings of the 2008 International Conference on Formal Methods in Computer-Aided Design
CODES+ISSS '09 Proceedings of the 7th IEEE/ACM international conference on Hardware/software codesign and system synthesis
Nucleos: a runtime system for ultra-compact wireless sensor nodes
EMSOFT '10 Proceedings of the tenth ACM international conference on Embedded software
Synchronous dataflow scenarios
ACM Transactions on Embedded Computing Systems (TECS)
IEEE Transactions on Signal Processing
Parameterized dataflow modeling for DSP systems
IEEE Transactions on Signal Processing
Shared buffer implementations of signal processing systems using lifetime analysis techniques
IEEE Transactions on Computer-Aided Design of Integrated Circuits and Systems
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This article presents a buffer minimization scheme with low dispatching overhead for embedded software processes. To accomplish this, we exploit behavioral transparency in the model of computation. In such a model (e.g., synchronous dataflow), the state of buffer requirements is determined completely by the firing sequence of the actors without requiring functional simulation of the actors. Fine-grained buffer allocation incurs high and code pointer overhead while coarse-grained allocation suffers from memory fragmentation. Instead, we propose a medium-grained, “access-contiguous” buffer allocation scheme that minimizes the total buffer space and pointer overhead. We formulate the buffer allocation problem as 2D tiles that represent the lifetime of the buffers to minimize their memory occupation spatially and temporally. Experimental results show that our scheme uses less data memory than existing techniques by 26% on average, or up to 57% in the best case. Our technique retains code modularity for dynamic configuration and, more importantly, enables many more applications that otherwise would not fit if implemented using previous state-of-the-art techniques.