Static scheduling of synchronous data flow programs for digital signal processing
IEEE Transactions on Computers
Joint Minimization of Code and Data for Synchronous DataflowPrograms
Formal Methods in System Design
Data memory minimisation for synchronous data flow graphs emulated on DSP-FPGA targets
DAC '97 Proceedings of the 34th annual Design Automation Conference
Minimizing Buffer Requirements under Rate-Optimal Schedule in Regular Dataflow Networks
Journal of VLSI Signal Processing Systems
Verification and Optimization of a PLC Control Schedule
Proceedings of the 7th International SPIN Workshop on SPIN Model Checking and Software Verification
Experience with Literate Programming in the Modelling and Validation of Systems
TACAS '98 Proceedings of the 4th International Conference on Tools and Algorithms for Construction and Analysis of Systems
Efficient Guiding Towards Cost-Optimality in UPPAAL
TACAS 2001 Proceedings of the 7th International Conference on Tools and Algorithms for the Construction and Analysis of Systems
Scheduling a Steel Plant with Timed Automata
RTCSA '99 Proceedings of the Sixth International Conference on Real-Time Computing Systems and Applications
Representing and Scheduling Looping Behavior Symbolically
ICCD '00 Proceedings of the 2000 IEEE International Conference on Computer Design: VLSI in Computers & Processors
Minimising buffer requirements of synchronous dataflow graphs with model checking
Proceedings of the 42nd annual Design Automation Conference
Proceedings of the 43rd annual Design Automation Conference
ACSD '06 Proceedings of the Sixth International Conference on Application of Concurrency to System Design
Efficient computation of buffer capacities for multi-rate real-time systems with back-pressure
CODES+ISSS '06 Proceedings of the 4th international conference on Hardware/software codesign and system synthesis
Liveness and Boundedness of Synchronous Data Flow Graphs
FMCAD '06 Proceedings of the Formal Methods in Computer Aided Design
Spin model checker, the: primer and reference manual
Spin model checker, the: primer and reference manual
Optimal scheduling using branch and bound with SPIN 4.0
SPIN'03 Proceedings of the 10th international conference on Model checking software
Buffer Optimization and Dispatching Scheme for Embedded Systems with Behavioral Transparency
ACM Transactions on Design Automation of Electronic Systems (TODAES)
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Synchronous Data flow (SDF) graphs have a simple and elegant semantics (essentially linear algebra) which makes SDF graphs eminently suitable as a vehicle for studying scheduling optimisations. We extend related work on using SPIN to experiment with scheduling optimisations aimed at minimising buffer requirements. We show that for a benchmark of commonly used case studies the performance of our SPIN based scheduler is comparable to that of state of the art research tools. The key to success is using the semantics of SDF to prove when using (even unsound and/or incomplete) optimisations are justified. The main benefit of our approach lies in gaining deep insight in the optimisations at relatively low cost.