Static scheduling of synchronous data flow programs for digital signal processing
IEEE Transactions on Computers
Introduction to algorithms
Supercompilers for parallel and vector computers
Supercompilers for parallel and vector computers
Scheduling synchronous dataflow graphs for efficient looping
Journal of VLSI Signal Processing Systems
Software synthesis for DSP using Ptolemy
Journal of VLSI Signal Processing Systems - Special issue on design environments for DSP
Compiling dataflow programs for digital signal processing
Compiling dataflow programs for digital signal processing
Optimizing Supercompilers for Supercomputers
Optimizing Supercompilers for Supercomputers
Dependence Analysis for Supercomputing
Dependence Analysis for Supercomputing
Software Synthesis from Dataflow Graphs
Software Synthesis from Dataflow Graphs
Computers and Intractability: A Guide to the Theory of NP-Completeness
Computers and Intractability: A Guide to the Theory of NP-Completeness
Memory efficient software synthesis form dataflow graph
Proceedings of the 11th international symposium on System synthesis
Shared memory implementations of synchronous dataflow specifications
DATE '00 Proceedings of the conference on Design, automation and test in Europe
Efficient code synthesis from extended dataflow graphs for multimedia applications
Proceedings of the 39th annual Design Automation Conference
Minimizing Buffer Requirements under Rate-Optimal Schedule in Regular Dataflow Networks
Journal of VLSI Signal Processing Systems
A Buffer Merging Technique for Reducing Memory Requirements of Synchronous Dataflow Specifications
Proceedings of the 12th international symposium on System synthesis
ACM Transactions on Design Automation of Electronic Systems (TODAES)
Multithreaded Synchronous Data Flow Simulation
DATE '03 Proceedings of the conference on Design, Automation and Test in Europe - Volume 1
Shift buffering technique for automatic code synthesis from synchronous dataflow graphs
CODES+ISSS '05 Proceedings of the 3rd IEEE/ACM/IFIP international conference on Hardware/software codesign and system synthesis
Proceedings of the 2005 international conference on Compilers, architectures and synthesis for embedded systems
Memory optimal single appearance schedule with dynamic loop count for synchronous dataflow graphs
ASP-DAC '06 Proceedings of the 2006 Asia and South Pacific Design Automation Conference
Efficient simulation of critical synchronous dataflow graphs
Proceedings of the 43rd annual Design Automation Conference
Efficient simulation of critical synchronous dataflow graphs
ACM Transactions on Design Automation of Electronic Systems (TODAES)
Memory-optimized software synthesis from dataflow program graphs with large size data samples
EURASIP Journal on Applied Signal Processing
Buffer optimization and dispatching scheme for embedded systems with behavioral transparency
EMSOFT '07 Proceedings of the 7th ACM & IEEE international conference on Embedded software
Minimizing Place Capacities of Weighted Event Graphs for Enforcing Liveness
Discrete Event Dynamic Systems
Scheduling optimisations for SPIN to minimise buffer requirements in synchronous data flow
Proceedings of the 2008 International Conference on Formal Methods in Computer-Aided Design
Minimizing communication in rate-optimal software pipelining for stream programs
Proceedings of the 8th annual IEEE/ACM international symposium on Code generation and optimization
Postscheduling buffer management trade-offs in streaming software synthesis
ACM Transactions on Design Automation of Electronic Systems (TODAES) - Special section on verification challenges in the concurrent world
Buffer Optimization and Dispatching Scheme for Embedded Systems with Behavioral Transparency
ACM Transactions on Design Automation of Electronic Systems (TODAES)
Hi-index | 0.00 |
In this paper, we formally develop techniques that minimize thememory requirements of a target program when synthesizing softwarefrom dataflow descriptions of multirate signal processingalgorithms. The dataflow programming model that we consider is thesynchronous dataflow (SDF)model [21], which has been used heavily in DSP design environmentsover the past several years. We first focus on the restricted classof well-ordered SDF graphs. We show that whileextremely efficient techniques exist for constructing minimum codesize schedules for well-ordered graphs, the number of distinctminimum code size schedules increases combinatorially with the numberof vertices in the input SDF graph, and these different schedules canhave vastly different data memory requirements. We develop a dynamicprogramming algorithm that computes the schedule that minimizes thedata memory requirement from among the schedules that minimize codesize, and we show that the time complexity of this algorithm is cubicin the number of vertices in the given well-ordered SDF graph. Wepresent several extensions to this dynamic programming technique tomore general scheduling problems, and we present a heuristic thatoften computes near-optimal schedules with quadratic time complexity.We then show that finding optimal solutions for arbitrary acyclicgraphs is NP-complete, and present heuristic techniques that jointlyminimize code and data size requirements. We present a practicalexample and simulation data that demonstrate the effectiveness ofthese techniques.