Software pipelining: an effective scheduling technique for VLIW machines
PLDI '88 Proceedings of the ACM SIGPLAN 1988 conference on Programming Language design and Implementation
Compiling dataflow programs for digital signal processing
Compiling dataflow programs for digital signal processing
Joint Minimization of Code and Data for Synchronous DataflowPrograms
Formal Methods in System Design
Computer architecture (2nd ed.): a quantitative approach
Computer architecture (2nd ed.): a quantitative approach
Software Synthesis from Dataflow Graphs
Software Synthesis from Dataflow Graphs
Multirate signal processing in Ptolemy
ICASSP '91 Proceedings of the Acoustics, Speech, and Signal Processing, 1991. ICASSP-91., 1991 International Conference
Multithreaded simulation for synchronous dataflow graphs
Proceedings of the 45th annual Design Automation Conference
Multithreaded Simulation for Synchronous Dataflow Graphs
ACM Transactions on Design Automation of Electronic Systems (TODAES)
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This paper introduces an efficient multithreaded synchronous dataflow (SDF) scheduler that can significantly reduce the running time of multi-rate SDF simulations on multiprocessor machines with only a slight increase of memory usage over standard cluster loop scheduler [1]. Experiments run on a dual processors machine achieves on average approximately 146% increase in performance with less than 2.4% increase in memory usage. There is an average of 2x speedup with a quad processors machine.