Data memory minimisation for synchronous data flow graphs emulated on DSP-FPGA targets

Authors:
Marleen Adé;Rudy Lauwereins;J. A. Peperstraete
Affiliations:
Katholieke Universiteit Leuven, ESAT Department, ACCA Laboratory, Kard. Mercierlaan 94, B-3001 Heverlee, Belgium;Katholieke Universiteit Leuven, ESAT Department, ACCA Laboratory, Kard. Mercierlaan 94, B-3001 Heverlee, Belgium;Katholieke Universiteit Leuven, ESAT Department, ACCA Laboratory, Kard. Mercierlaan 94, B-3001 Heverlee, Belgium
Venue:
DAC '97 Proceedings of the 34th annual Design Automation Conference
Year:
1997

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Abstract

The paper presents an algorithm to determine the close-to-smallestpossible data buffer sizes for arbitrary synchronous dataflow (SDF) applications, such that we can guarantee the existenceof a deadlock free schedule. The presented algorithm fits inthe design flow of GRAPE, an environment for the emulation andimplementation of digital signal processing (DSP) systems onarbitrary target architectures, consisting of programmable DSPprocessors and FPGAs. Reducing the size of data buffers is ofhigh importance when the application will be mapped on FieldProgrammable Gate Arrays (FPGA), since register resources arerather scarce.