Fractional Rate Dataflow Model for Efficient Code Synthesis

  • Authors:

  • Hyunok Oh;Soonhoi Ha

  • Affiliations:

  • School of Computer Science and Engineering, Seoul National University, Sinlimdong, Kwanakgu, Seoul 151-742, Korea;School of Computer Science and Engineering, Seoul National University, Sinlimdong, Kwanakgu, Seoul 151-742, Korea

  • Venue:
  • Journal of VLSI Signal Processing Systems
  • Year:
  • 2004

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Abstract

Automatic code synthesis from dataflow program graphs is a promising high-level design methodology for rapid prototyping of multimedia embedded systems. Memory efficient code synthesis from dataflow models has been an active research subject to reduce the gap in terms of memory requirements between the synthesized code and the hand-optimized code. However, existent dataflow models have inherent difficulty of efficiently handling data structures. In this paper, we propose a new dataflow extension called fractional rate dataflow (FRDF) in which fractional number of samples can be produced and consumed. In the proposed FRDF model, a constituent data type is considered as a fraction of the composite data type. Existent integer rate dataflow models can be easily extended to incorporate the fractional rates without loosing analytical properties. In this paper, the SDF model is extended to include FRDF, which can reduce the buffer memory requirements significantly, up to 70%, for some multimedia applications. Extended SDF model with fractional rate has been implemented in our system design environment called PeaCE(Ptolemy extension as Codesign Environment).