Parameterized Scheduling of Topological Patterns in Signal Processing Dataflow Graphs

Authors:
Lai-Huei Wang;Chung-Ching Shen;Shenpei Wu;Shuvra S. Bhattacharyya
Affiliations:
Department of Electrical and Computer Engineering,and Institute for Advanced Computer Studies, University of Maryland, College Park, USA 20742;Department of Electrical and Computer Engineering,and Institute for Advanced Computer Studies, University of Maryland, College Park, USA 20742;Department of Electrical and Computer Engineering,and Institute for Advanced Computer Studies, University of Maryland, College Park, USA 20742;Department of Electrical and Computer Engineering,and Institute for Advanced Computer Studies, University of Maryland, College Park, USA 20742
Venue:
Journal of Signal Processing Systems
Year:
2013

Citing 12
Cited 0

Fractional Rate Dataflow Model for Efficient Code Synthesis

Journal of VLSI Signal Processing Systems
Distinctive Image Features from Scale-Invariant Keypoints

International Journal of Computer Vision
Reactive process networks

Proceedings of the 4th ACM international conference on Embedded software
Modeling and FPGA Implementation of Applications Using Parameterized Process Networks with Non-Static Parameters

FCCM '05 Proceedings of the 13th Annual IEEE Symposium on Field-Programmable Custom Computing Machines
Software synthesis from the dataflow interchange format

SCOPES '05 Proceedings of the 2005 workshop on Software and compilers for embedded systems
Exploring the concurrency of an MPEG RVC decoder based on dataflow program analysis

IEEE Transactions on Circuits and Systems for Video Technology
Handbook of Signal Processing Systems

Handbook of Signal Processing Systems
A design tool for efficient mapping of multimedia applications onto heterogeneous platforms

ICME '11 Proceedings of the 2011 IEEE International Conference on Multimedia and Expo
Parameterized Looped Schedules for Compact Representation of Execution Sequences in DSP Hardware and Software Implementation

IEEE Transactions on Signal Processing
Cycle-static dataflow

IEEE Transactions on Signal Processing
Parameterized dataflow modeling for DSP systems

IEEE Transactions on Signal Processing
Optimal decoding of linear codes for minimizing symbol error rate (Corresp.)

IEEE Transactions on Information Theory

Quantified Score

Hi-index	0.00

Visualization

Abstract

In recent work, a graphical modeling construct called "topological patterns" has been shown to enable concise representation and direct analysis of repetitive dataflow graph sub-structures in the context of design methods and tools for digital signal processing systems (Sane et al. 2010). In this paper, we present a formal design method for specifying topological patterns and deriving parameterized schedules from such patterns based on a novel schedule model called the scalable schedule tree. The approach represents an important class of parameterized schedule structures in a form that is intuitive for representation and efficient for code generation. Through application case studies involving image processing and wireless communications, we demonstrate our methods for topological pattern representation, scalable schedule tree derivation, and associated dataflow graph code generation.