Test strategies for BIST at the algorithmic and register-transfer levels
Proceedings of the 38th annual Design Automation Conference
TAO: regular expression-based register-transfer level testability analysis and optimization
IEEE Transactions on Very Large Scale Integration (VLSI) Systems - System Level Design
TAO: regular expression based high-level testability analysis and optimization
ITC '98 Proceedings of the 1998 IEEE International Test Conference
Non-Scan Design for Testability for Synchronous Sequential Circuits Based on Conflict Analysis
ITC '00 Proceedings of the 2000 IEEE International Test Conference
Nonscan Design for Testability for Synchronous Sequential Circuits Based on Conflict Resolution
IEEE Transactions on Computers
A synthesis-for-transparency approach for hierarchical and system-on-a-chip test
IEEE Transactions on Very Large Scale Integration (VLSI) Systems
Low test application time resource binding for behavioral synthesis
ACM Transactions on Design Automation of Electronic Systems (TODAES)
High-level test synthesis for delay fault testability
Proceedings of the conference on Design, automation and test in Europe
High-level test synthesis with hierarchical test generation for delay-fault testability
IEEE Transactions on Computer-Aided Design of Integrated Circuits and Systems
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In recent years, there has been growing interest in behavioral (high-level) synthesis for testability. This is due to the fact that testability features, such as scan or the built-in self-test, may incur large overheads if introduced during logic synthesis in the later phase of the design cycle. Related previous work attempted to generate system-level test sets using hierarchical testability during behavioral synthesis. There, the test generation scheme is independent of bit width and is, therefore, capable of handling complex controller/data path circuits with large data path bit widths (e.g., 32), which has posed a serious challenge to logic-level sequential test generators. However, this previous work is not applicable when another high-level synthesis system is used. In this paper, we present techniques that add minimal test hardware to a given register-transfer level (RTL) circuit obtained by behavioral synthesis in order to ensure that the embedded elements in the circuit are hierarchically testable. An important byproduct of our design for testability (DFT) procedure is a system-level test set that delivers precomputed test sets to each element in the RTL circuit. This eliminates the need to apply gate-level sequential test generation to the combined controller/data path. We performed extensive experiments with several complex controller/data path circuits synthesized by three different high-level synthesis systems which do not target testability. The key advantages of our method, illustrated by these experiments, include: 1) the area, delay, and power overheads incurred for testability are very low (the average area, delay, and power overheads for a large number of benchmarks are 3.5, 0.5, and 3.4%, respectively), 2) both the DFT hardware addition and test generation algorithms are independent of the data path bit width