Enhancing high-level control-flow for improved testability
Proceedings of the 1996 IEEE/ACM international conference on Computer-aided design
Behavioral Testability Insertion for Datapath/Controller Circuits
Journal of Electronic Testing: Theory and Applications - Special issue on test synthesis
A BIST scheme for RTL controller-data paths based on symbolic testability analysis
DAC '98 Proceedings of the 35th annual Design Automation Conference
IEEE Transactions on Very Large Scale Integration (VLSI) Systems
Testability Enhancement for Control-Flow Intensive Behaviors
Journal of Electronic Testing: Theory and Applications
Channel-based behavioral test synthesis for improved module reachability
DATE '99 Proceedings of the conference on Design, automation and test in Europe
Hierarchical Test Generation Based on Delayed Propagation
Proceedings of the IEEE International Test Conference on Test: Faster, Better, Sooner
Test Propagation Through Modules and Circuits
Proceedings of the IEEE International Test Conference on Test: Faster, Better, Sooner
TAO: regular expression based high-level testability analysis and optimization
ITC '98 Proceedings of the 1998 IEEE International Test Conference
Breaking Correlation to Improve Testability
VTS '01 Proceedings of the 19th IEEE VLSI Test Symposium
Design for hierarchical testability of RTL circuits obtained by behavioral synthesis
IEEE Transactions on Computer-Aided Design of Integrated Circuits and Systems
A Self Test Program Design Technique for Embedded DSP Cores
Journal of Electronic Testing: Theory and Applications
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The proposed BIST-based DFT method target testability problems caused by three constructs. The first construct is reconvergent fanout in a circuit behavior, which causes correlation. The second construct, control statements, also cause correlation and relational operations degrade observability. The third construct is random-pattern-resistant RTL modules, which cannot be tested effectively with random patterns. Test strategies are presented that overcome the testability problems by modigying the circuit behavior. An analysis and insertion scheme that systematically identifies the problems and applies the strategies is described. Experimental results from seven examples show that this scheme improves fault coverage while minimizing the impact on area and critical delay.