Partial Scan Design Based on Circuit State Information and Functional Analysis
IEEE Transactions on Computers
Eliminating the Timing Penalty of Scan
Journal of Electronic Testing: Theory and Applications
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This paper addresses the problem of flip flop selection for partial scan in sequential circuits. In particular it addresses some of the shortcomings of the popular flip flop selection methods, based on cutting cycles present in the graph of the circuit structure. Previous approaches assume that cutting all cycles makes the circuit totally testable, which is not always true. In the proposed approach, first subsets of flip flops are formed based on cycles in the S-graph and flip flops with self-loops. Flip flops are selected from these subsets based on a testability measure which uses an approximate valid state analysis. Once a flip flop is selected from a subset, testability measures may indicate the need for more flip flops, thus possibly selecting more flip flops than required for minimum cycle cutting. The goal is to select the fewest number of flip flops required to obtain high fault coverage for all partial scan circuits. Experimental results on the benchmark circuits show that a test generation efficiency near 100 is achieved for most circuits.